This invention relates to semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry.
Integrated memory devices typically include a memory array area and a peripheral circuitry area. The memory array area constitutes the area in which information or data is stored. The peripheral circuitry area constitutes integrated circuitry which, in part, controls or provides access to the memory array area. One type of integrated memory device is a dynamic random access memory (DRAM) device. DRAMs include, as part of the memory array, plural capacitors which are used to store charges. It is desirable to fabricate integrated circuitry memory devices to have fairly close, comparable, and repeatable capacitance values.
Stacked DRAM capacitors are typically formed from a plurality of layers provided over a substrate by etching at least some of the layers to form a desired capacitor container construction. Capacitors are thereafter formed in the etched containers. To increase the capacitance values of the subsequently formed capacitors, a timed etch is typically conducted to further etch the provided layers after an initial capacitor container definition etch is conducted. Such timed etches can be problematic for a number of reasons. For example, such etches must be carefully monitored and timed to ensure that the etch does not undesirably extend into adjacent integrated device components, which can destroy the circuit. Thus, control of the etches is of major concern. Another problem is that reproducibility of the depth of such etches can be difficult to attain given variations in the processing regimes and materials used to fabricate the capacitor containers. Thus, a need exists for semiconductor processing methods which enable memory devices to be fabricated with predictable and readily reproducible capacitance values.
Another problem associated with the fabrication of integrated memory devices concerns forming electrical connections between conductive lines and substrate active areas in peripheral circuitry areas of the memory array. More specifically, it is sometimes desirable for conductive lines to be electrically connected with substrate active areas which are disposed elevationally lower over a substrate than the respective conductive lines. Typically, the elevational separation between the conductive lines and the substrate active area is due to one or more layers which are interposed between the conductive lines and the corresponding active area to which electrical connection is desired. Often such conductive lines do not typically directly overlie the entire active area with which electrical connection is desired. One prior art solution is to provide a conductive plug of material which extends generally vertically between and connects with the overlying conductive line and only a portion of the active area with which electrical connection is desired. This, however, gives rise to increased resistance and hence lower conductivity as between the conductive line and the elevationally lower substrate active area. Thus, a need exists to provide improved semiconductor processing methods and related integrated circuitry formed thereby with improved conductive connections between elevationally separated conductive lines and substrate active areas.
This invention arose out of concerns associated with forming integrated memory circuitry, particularly DRAM memory devices, with standardized and readily reproducible component values, as well as improving conductive connections between the memory device components.
In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductively doped layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductively doped layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductively doped layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductively doped layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide.
In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate. The upper insulating layer is etched relative to the interposed conductive layer to form a capacitor container first portion. Subsequently, the interposed conductive layer is etched to form a capacitor container second portion. Preferably, the first etch is substantially selective relative to the interposed conductive layer. Additionally, the second etch is preferably substantially selective relative to the lower conductive layer.
According to another preferred implementation, the invention provides a method of forming capacitor containers. According to a preferred implementation, at least three layers of different materials are formed over a substrate and subsequently etched to form a desired capacitor container. According to a preferred aspect, a first of the materials is etched using a first etching composition which outwardly exposes at least some of a second of the materials. Preferably, such exposure is detected whereupon the first etching composition is changed to a second etching composition which is different from the first etching composition. Accordingly, and utilizing the second etching composition, the second of the materials is etched to outwardly expose at least some of a third of the materials.